The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, light diffraction in an optical lithography system becomes an obstacle for further scaling down the geometry size. Common techniques used to decrease the light diffraction impact, include optical proximity correction (OPC), phase shift mask (PSM), and immersion optical lithography system. An electron beam lithography system is another alternative to scale down the feature size. However, wafer throughput by electron beam lithography system is a major issue for large scale fabrication in the IC industry.
Accordingly, what is needed is a method to increase the wafer throughput for the electron beam lithography system.